Verilog程序12、VGA显示字符(5)

Verilog程序

always @(posedge clk)

if(!valid)

vga_rgb <= 8'h00;

else if(x_pos > 10'd384 && x_pos <= 10'd416) begin

case(y_pos)

10'd292: if(line0[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd293: if(line1[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd294: if(line2[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd295: if(line3[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd296: if(line4[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd297: if(line5[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd298: if(line6[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd299: if(line7[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd300: if(line8[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd301: if(line9[char_bit]) vga_rgb <= 8'b111_000_00;