AT24C164-10PU-2.7中文资料(6)

元器件交易网

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (refer toData Validity timing diagram). Data changes during SCL high periods will indicate a startor stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start conditionwhich must precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby powermode (see Figure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and fromthe EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it hasreceived each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C164 features a low power standby mode which isenabled: a) upon power-up and b) after the receipt of the STOP bit and the completionof any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, theAT24C164 can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then(c) create a start condition as SDA is high.

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AT24C164

0105J–SEEPR–12/06