边缘检测电路的(SOC)(Verilog)(6)

边缘检测电路的硬件实现,用的是Verilog语言,采用的是原理图输入,给出了源代码,对于采用FPGA做图像预处理有着很好的参考价值

Method 1：

使用兩個reg nededge_detection.v / Verilog

1 /*

2 (C) OOMusou 2008

3

4 Filename : nededge_detection.v

5 Compiler : Quartus II 7.2 SP3

6 Description : Demo how to design nededge detection circuit 7 Release : 07/06/2008 1.0

8 */

9 module negedge_detection (

10 input clk,

11 input rst_n,

12 input i_data_in,

13 output o_falling_edge

14 );

15

16 reg r_data_in0;

17 reg r_data_in1;

18

19 assign o_falling_edge = r_data_in0 & ~r_data_in1;

20

21 always@(posedge clk, negedge rst_n) begin

22 if (!rst_n) begin

23 r_data_in0 <= 0;

24 r_data_in1 <= 0;

25 end

26 else begin

27 r_data_in0 <= r_data_in1;

28 r_data_in1 <= i_data_in;

29 end

30 end

31

32 endmodule

Method 2：

使用1個reg

nededge_detection2.v

1 /*