宽带直流放大器论文(15)

case current_state is when st0=> wr<='0';

next_state<=st1; when st1=> wr<='1';

next_state<=st2; when st2=>

if(int='0') then next_state<=st2; elsif int='1' then next_state<=st3; end if; when st3=>

if int='1' then next_state<=st3; elsif int='0' then next_state<=st4; end if; when st4=> wr<='0'; d_mid<=d_in; next_state<=st5; when st5=>

next_state<=st0; when others=> null; end case; end process com; end behav;