Fault Sensitivity Analysis and Reliability Enhancement of An(10)

Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a

9876

Delay (ns)

5432100

2

4

6

8

10

12

14

16

(ARE)(ARE)TABLEIX

-ΣADC(NFTVSFT)

SENSITIVITY,

p=2,q=8,r=16

Resistance (in K)

Fig.28.r=32

Variationinperformancewithincreasingresistance(R),p=3,q=8,

(ARE)(ARE)TABLEVIII

DIGITALDECIMATIONFILTERSENSITIVITYOFTHENONFAULTTOLERANT(NFT)ANDTHEFAULTTOLERANT(FT)VERSIONS,p=2,

q=8,r=4

Fig.29. -Σmodulatorwithredundancy

tationandhencemaynotbeaneffectivereplacementfortheconventionalimplementation.

3)SuccessiveApproximationADC:Thesensitivityanaly-sisofthe4-bitSAADChasidenti edtheconvertlatchandtheoutputlatchascriticalblocks.TheTransientPulseToler-antLatch(TPTL)proposedin[24]wasconsideredforreliabil-ityimprovement.TheresistorsintheTPTL lteroutthetran-sientsarrivingattheinputofthelatchthushardeningitagainsttransients.Withincreasingvaluesoftheresistors,thelatchbe-comesmorefaulttolerantbutatthesametimeaperformancepenaltyisincurred[17](Figure27).Theoverheadcanbere-ducedbyreplacingonlythemostsensitivelatchinconvertlatchbyTPTL.

Figure28showsthatthedelayduetohigherresistancein-creasesexponentially.Therefore,the nalresistancevalueshouldbechosenbytakingtheperformancedegradationintoaccount.

4) -ΣADC:Sincethedigitaldecimation lterinthe -ΣADCuseslatchesextensively,usingtheTPTLdescribedintheprevioussubsectioncanlowerthesensitivityofthedecima-tion lter.Wetherefore,replacedalllatcheswithTPTLandobservedimprovementsinsensitivitiesofasmuchas21%(Ta-blesVIIIandIX).Thisimprovementisachievedhowever,atacostofreducedperformance.Figure28showstheperformancedegradationduetointroductionoftheresistance(R).B.AddingRedundancy

Whereastheprevioustechniquetendstowardsfaultre-silience,thistechniqueattemptstomasktheeffectofafault.Oneofthewaysfaulttolerancecanbeachievedthroughre-dundancyisto rstdetectthefaultandthenrecoverfromthefault.Thisinvolvesduplicationoftheblock,anddesignofan

(ARE)OF

(ARE)TABLEX

SENSITIVITY(×10 4)ANDMRE

-ΣMODULATOR,p=3,q=8,r=16

errordetectionschemewhichcanactivatetheredundantblockwhenafaultisdetected.Thistechniquehasbeenimplementedforthemodulatorinthe -ΣADC.The -Σmodulatorisanidealcandidateforapplyingthistechniquebecausethetech-niqueaddressestheintegratorwhichisauto-zeroedonthedec-imatedclock(T3inFigure29).Iftheerrorisnotcorrecteditwilleffectthesubsequentserialbitstreamgeneratedanditwillgenerateerroneousbitstillthenexttimetheintegratorisauto-zeroed.ThoughthistechniquecanbeusedforotherADCs,itwillhavethemaximumimpactonADCslikethe -Σ,partofwhichretainssomeinformationfromthepreviouscycle(liketheintegrator).

Whiletheinputisbeingsampledontothesamplingcapaci-tor,therestofthenodesintheADCaremaintainedatthevalueevaluatedinthepreviouscycle.Thischaracteristiccanbeusedtodetectanerrorandprotectthecircuitfromfaultsinjectedduringthesamplingtime.Sincerecent -ΣADCimplemen-tationsshowthatalmost50%[18]ofthecycletimeisspentinsampling,thisschemewouldaddressasizeablenumberoffaults.Thisfactfurtherforti estheargumentthattheproposedtechniqueisbettersuitedtothe -ΣADCascomparedtootherADCs.Figure29showsthemodi ed rst-order -Σmodula-torwiththeredundancyincorporatedinit.ThecapacitorC1