Fault Sensitivity Analysis and Reliability Enhancement of An(7)

Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a

Fig.17.BlocksensitivityvariationwithinputsfortheSAADC,q=14,r

=32

Fig.20.Maximumrelativeerror(SA),p=3,q=14,r=32

outputlatch

sha

0.1

0.0090.008

0.01

0.0070.006POF

2

0.001

0.0050.004

1e 05

Charge injected (pC)

468

0.0030.002

01

Bit Position

23

Fig.18.

r=32

Blocksensitivities(logscale)variationwithinjections(SA),p=3,

Fig.21.Sensitivityofthefourlatchesinconvertlatch(SA),p=3,q=14,r=32

0.080.070.060.05

-ΣADC

POF

0.040.030.020.0100

TABLEIV

SENSITIVITYANALYSIS,

p=2,q=8,r=16

sampleBit4Bit3Bit2Bit1readout

Injection Time

Fig.19.VariationofPOFwithfaultinjectiontimes(SA),p=3,q=14

tionlevelstheorderingofcriticalblocksmightchange(SHAismoresensitivethantheoutputlatchfrom0pCto0.25pC).This gurealsoshowsthat,asfortheFIADC,beyondacertainin-jectionlevelthereisnofurtherincreaseinthesensitivityoftheblocksintheSAADC.Figure19showsthevariationinsensi-tivitywithfaultsinjectedatdifferenttimeinstancesforasuc-cessiveapproximationADC.TheresultsindicatethattheADCismoresusceptibletoα-particlehitsduringtheearlypartofeachbitconversioncycle.Figure20showsthemaximumrel-ativeerrorduetoeachblock.Ourresultsindicatethataswegettoblocksclosertotheinput,themaximumrelativeerrorin-creases,reachinga

peakforthesampleandholdampli ers(shainFigure20).Anotheranalysisperformedontheconvertlatchrevealedthatoutofthefourlatchesintheconvertlatch,thelatchcontainingthemostsigni cantbitisthemostsensitive(Figure21).Theoutputlatch,convertlatchandshahavebeenthusiden-ti edascriticalblocksthatshouldberedesignedtoimprovethereliabilityofthecircuit.

4) -ΣADC:The -ΣADCliketheSAADCtakessev-eralcyclestogeneratethe nalADCoutput.Thenumberofcyclesrequiredtogeneratethe naloutputisgovernedbytheoversamplingratioofthe -Σconverter.Forthe4-bit -ΣADCimplementedforthiswork,the -Σmodulatorgenerateseightbitsin8clockcycles.Theseeightbitsarethendigitally lteredandthe nal4-bitADCoutputisgeneratedatadeci-matedfrequency.Themiddlebits(bit3to6)amongtheeightbitsgeneratedbythe -Σmodulatorcontributemoretowardsthe nalADCoutputasthelarger ltercoef cientsaremulti-pliedbythesebits.However,thesebitsarenotnecessarilythemostsensitiveones.Therefore,itisofinteresttoanalyzethenumberoferrorsineachoftheeightbitsresultingfrominjec-tionsinthe -Σmodulator.Figure22showsthevariationofthenumberoferrorswithbitsgeneratedinthe rsttotheeighthclockcycles.Itisobservedthatthebitsgeneratedinthelatercyclesaremorepronetofaults.Thiscanbeattributedtothefactthatthebitgeneratedinthenthcycleisdependentontheoffsetstoredintheintegratorinthe(n 1)thcycle.Therefore,thebitgeneratedinthelastcycle(inthiscasethe8thcycle)willbesensitivetofaultsinjectedinallprecedingcyclesinadditiontothoseinjectedinthecurrentcycle.Asensitivityanalysisof