MAX1310ECM中文资料(5)

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF = VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+ =CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-lar devices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA= TMINto TMAX,unless otherwise noted. Typical values are at TA= +25°C. See Figures 3 and 4.)

MAX1312/MAX1313/MAX1314, VIN= -10V to +10V.

Note 2:All channel performance is guaranteed by correlation to a single channel test.

Note 3:The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:

ICH_=

VCH_ VBIAS

RCH_

for VCHwithin the input voltage range.

Note 4:Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK). The external clock through-put rate is specified with fCLK= 16.67MHz and the internal clock throughput rate is specified with fCLK= 15MHz. See theData Throughputsection for more information.

Note 5:The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:

IREF=

VREF 2.5V

RREF

for VREFwithin the input voltage range.

Note 6:The REFMSinput resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REFMSinput current using:

IREFMS=

VREFMS 2.5V

RREFMS

for VREFMSwithin the input voltage range.

Note 7:All analog inputs are driven with a -0.4dBFS 500kHz sine wave.

Note 8:Shutdown current is measured with the analog input floating. The large amplitude of the maximum shutdown current speci-fication is due to automated test equipment limitations.

Note 9:CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.Note 10:CSto WRand CSto RDare internally AND together. Setup and hold times do not apply.

Note 11:Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST

and the falling edge of EOLCto a maximum of 1ms.

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元器件交易网

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsTypical Operating Characteristics

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolardevices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), fIN= 500kHz, AIN= -0.4dBFS. TA= +25°C,unless otherwise noted.) (Figures 3 and 4)

INTEGRAL NONLINEARITYDIFFERENTIAL NONLINEARITYvs. DIGITAL OUTPUT CODE

vs. DIGITAL OUTPUT CODE

1.01

1.0

2

00ccoot t40.8 4000.83311XXA0.6AM0.6M0.40.4)

)

BB0.2S0.2SLL( ( L0L0NNDI-0.2-0.2-0.4-0.4-0.6-0.6-0.8-0.8-1.0

-1.0

5121024153620482560307235844096

5121024153620482560307235844096

DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE

OFFSET ERROR

OFFSET ERRORvs. ANALOG SUPPLY VOLTAGE

vs. TEMPERATURE

1.016

0.8120.6)

8B)

S0.4BLS( LR0.2(4 ORRORRE0R0 TE ETS-0.2EFSFF-4O-0.4FO-0.6-8-0.8-12

-1.0

-164.7

4.8

4.9

5.05.1

5.2

5.3

-40

-15

10

35

60

85

AVDD (V)

TEMPERATURE (°C)

GAIN ERROR

GAIN ERRORvs. ANALOG SUPPLY VOLTAGE

vs. TEMPERATURE

116

1208

)

B)

S-1BLS(L4 (R ORROR-2R0ER EN INAIG-3A-4G-8-4-12-5-164.7

4.8

4.9

5.05.1

5.2

5.3

-40

-15

10

35

60

85

AVDD (V)

TEMPERATURE (°C)

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MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314