A Generic Low Power Scan Chain Wrapper20121130

A Generic Low Power Scan Chain Wrapper for Designs Using Scan CompressionSabne, A.; Tiwari, R.; Shrivastava, A.; Ravi, S.; Parekhji, R. , “A Generic Low Power Scan Chain Wrapper for Designs Using Scan Copression”, VLSI Test Symposium (VTS), pp. 135-140, 2010 28th

CHENG Jun KIMURA LAB 2012/11/30

Outline Introduction A Low Power Scan Chain Wrapper Evaluation of the Proposed Architecture Methodology for Managing Configurability Silicon Power Measurements Conclusions

1. Introduction Test power consumption is becoming a major concern in low power ICs. Various techniques for lowering test mode power proposed, but many are not applicable to circuits employ test data compression. This paper examines a scalable, low design effort technique that can address the issues and help reduce peak switching during scan based testing.3

1.1 Related Work Fill techniques– Reduce toggle activity by filling don’t care bits in test stimuli. However, not as effective when using scan data compression.

Skewed clocking– Effective solution to reduce peak switching. But dynamic IR drop issues are not benefited unless at fine-grained level.

Scan chain segmentation– Divide scan chains into segments.

Capture power reduction through clock gate activation controls Shift frequency reduction– Useful in reducing average shift power consumption, but not in peak toggling.

Scan cell Q-gating– Aims at reducing the combinational circuit toggling during shift.4

1.2 Paper Overview and Contribution Two goals– Works in the presence of scan compression; – Works without requirements on chip clocking.

Our solution, a low power enabling scan chain wrapper, is based on two classical low-power DFT knobs:– Scan chain isolation: Provide hardware support to include or bypass scan chains. – Constant value propagation through isolated scan chains: Shift constant value (0 or 1) into the bypassed scan chains so that the corresponding flip-flops are subject to 0->0 or 1->1 transitions during scan stimuli shift operation.

Since the resulting modifications can be localized to a wrapper, the solution requires no internal changes to the compression logic and hence, can be made to work with any off-the-shelf test compression and ATPG tool.5

2. A Low Power Scan Chain Wrapper 2.1 Background – The test compression architecture primarily consists of two components: (i) Compactor-decompressor structure (often referred to as codec) to which the design scan chains are hooked up as shown. (ii) Codec controls (static and/or active) that come from a test subsystem.

2.2 Proposed Architecture An effective way to reduce test power consumption is– Gate off clocks to scan chains that are not in use as, in scan chain partitioning or segmentation.

Big challenge is the requirement on clocking control for segments of scan chains.– Workaround: not rely on clock gating, but on dat

a fill to reduce test power.

Figure 2 shows the wrapper for a scan chain to perform this function.

Scan chain wrapper Figure 2(a) consists of a scan flip-flop and two multiplexors that perform two main functions:– Normal mode of operation: when group_byp is ‘0’, the design chain appears between the “From Codec” and “To Codec” ports shown.

– Low power mode of operation: when group_byp is ‘1’ , The design chain is excluded from the codec STUMPS chains. To ensure that the excluded chain can be placed in a low power mode (without any clock gating requirements), we load ‘0’s into that scan chain. Assuming scan stitching is done with a no scan inversion policy, this ensures that all the flip-flops in the design scan chain only undergo ‘0’->‘0’ transition, thereby reducing the test power consumption.9

2.3 Expected benefits Figure (a) shows a typical test power profile for scan patterns. Switching power is very high during the first few patterns, then remains steady, and is very low for the last few patterns.a

Figure (b) shows the expected power profile from the architecture proposed. N1~N4 are different configurations containing different and decreasing numbers of scan chains bypassed(N1 most, N4 least).

b

2.4 Implementation in a 65nm SoC