MSP430 Programming Via the Bootstrap Loader

TI官方应用笔记

MSP430Programming Via the Bootstrap Loader User's Guide

Literature Number:SLAU319A

July2010–Revised August2010

TI官方应用笔记

2SLAU319A–July2010–Revised August2010

Copyright©2010,Texas Instruments Incorporated

TI官方应用笔记

Contents 1Programming Via the Bootstrap Loader (7)

1.1Supplementary Online Information (7)

1.2Introduction (7)

1.3Standard RESET and BSL Entry Sequence (8)

1.3.1MSP430Devices With Shared JTAG Pins (8)

1.3.2MSP430Flash Devices With Dedicated JTAG Pins (9)

1.3.3Devices With USB (9)

1.4UART Protocol (9)

1.5USB Protocol (9)

2ROM-Based Bootstrap Loader Protocol (11)

2.1Synchronization Sequence (11)

2.2Commands (11)

2.2.1Unprotected Commands (11)

2.2.2Password Protected Commands (11)

2.3Programming Flow (12)

2.4Data Frame (13)

2.4.1Data-Stream Structure (13)

2.4.2Checksum (14)

2.4.3Example Sequence (14)

2.4.4Commands–Detailed Description (14)

2.5Loadable BSL (18)

2.6Exiting the BSL (19)

2.7Password Protection (19)

2.8Code Protection Fuse (20)

2.9BSL Internal Settings and Resources (20)

2.9.1Chip Identification and BSL Version (20)

2.9.2Vectors to Call the BSL Externally (20)

2.9.3Initialization Status (21)

2.9.4Memory Allocation and Resources (22)

3Flash-Based Bootstrap Loader Protocol (23)

3.1BSL Data Packet (23)

3.2UART Peripheral Interface(PI) (23)

3.2.1Wrapper (23)

3.2.2Abbreviations (23)

3.2.3Messages (24)

3.2.4Interface Specific Commands (24)

3.3USB Peripheral Interface (24)

3.3.1Wrapper (24)

3.3.2Hardware Requirements (25)

3.4BSL Core Command Structure (25)

3.4.1Abbreviations (25)

3.4.2Command Descriptions (26)

3.5BSL Security (27)

3.5.1Protected Commands (27)

3.5.2RAM Erase (27)

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http://

3.6BSL Core Responses (28)

3.6.1Abbreviations (28)

3.6.2BSL Core Messages (29)

3.6.3BSL Version Number (29)

3.6.4Example Sequences for UART BSL (30)

3.7BSL Public Functions and Z-Area (30)

3.7.1Starting the BSL From an External Application (30)

3.7.2Function Description (30)

4Bootstrap Loader Hardware (31)

4.1Hardware Description (31)

4.1.1Power Supply (31)

4.1.2Serial Interface (32)

4.1.3Target Connector (33)

4.1.4Parts List (34)

5Differences Between Devices and Bootstrap Loader Versions (35)

5.15xx/6xx BSL Versions (35)

5.2Special Consideration for ROM BSL Version1.10 (36)

5.3ROM BSL Known Issues (36)

5.4Special Note on the MSP430F14x Device Family BSL (44)

6Bootstrap Loader PCB Layout Suggestion (45)

4Contents SLAU319A–July2010–Revised August2010

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http://

List of Figures

1-1.Standard RESET Sequence (8)

1-2.BSL Entry Sequence at Shared JTAG Pins (8)

1-3.BSL Entry Sequence at Dedicated JTAG Pins (9)

4-1.Bootstrap Loader Interface Schematic (31)

6-1.Universal BSL Interface PCB Layout,Top (45)

6-2.Universal BSL Interface PCB Layout,Bottom (45)

6-3.Universal BSL Interface Component Placement (46)

6-4.Universal BSL Interface Component Placement (47)

List of Tables

2-1.Data Frame of BSL Commands (13)

2-2.Recommendations for MSP430F149['F449](T

A =25°C,V

CC

=3.0V,f

max

=6.7MHz) (17)

2-3.Recommendations for MSP430F2131(T

A =25°C,V

CC

=3.0V,f

max

=6.7MHz) (17)

3-1.UART Protocol Interface (23)

3-2.UART Error Messages (24)

http://B Peripheral Interface (24)

3-4.BSL Core Commands (25)

3-5.BSL Core Responses (28)

3-6.BSL Core Messages (29)

4-1.Serial-Port Signals and Pin Assignments (32)

4-2.RS-232Levels (32)

4-3.Pin Assignment of Target Connector (33)

4-4.Universal BSL Interface Parts List (34)

5-1.BSL Version1.10on'F13x,'F14x(1)(excluding Rev AA),'F11x,and'F11x1 (37)

5-2.BSL Version1.30on'F41x,'F11x,and'F11x1 (38)

5-3.BSL Version1.40on'F12x (39)

5-4.BSL Version1.60on'F11x2,'F12x2,'F43x,'F44x,'FE42x,'FW42x,'F(G)43x,'F415,'F417 (40)

5-5.BSL Version1.61on'F16x,'F161x,'F42x0,'F13x rev AA,'F14x(1)rev AA (41)

5-6.BSL Version2.02on'F21xx,'F22xx,'F24x,'F23x (42)

5-7.BSL Version2.12/2.13on'FG46xx,'F261x,'F471xx (43)

5 SLAU319A–July2010–Revised August2010List of Figures

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6List of Tables SLAU319A–July2010–Revised August2010

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Chapter1

SLAU319A–July2010–Revised August2010

Programming Via the Bootstrap Loader The MSP430BSL enables users to communicate with embedded memory in the MSP430microcontroller during the prototyping phase,final production,and in service.Both the programmable memory(flash memory)and the data memory(RAM)can be modified as required.Do not confuse the bootstrap loader with programs found in some digital signal processors(DSPs)that automatically load program code(and data)from external memory to the internal memory of the DSP.These programs are often referred to as bootstrap loaders as well.

To use the bootstrap loader,a specific BSL entry sequence must be applied.An added sequence of commands initiates the desired function.A boot-loading session can be exited by continuing operation at a defined user program address or by the reset condition.

If the device is secured by disabling JTAG,it is still possible to use the BSL.Access to the MSP430 memory via the BSL is protected against misuse by a user-defined password.

1.1Supplementary Online Information

As a compliment to this document,a BSL wiki page is available.This wiki contains links to additional BSL projects,information,and an errata for this document.The wiki can be found at

http:///index.php/BSL_(MSP430).

A zip file with additional information,executables,and code samples can be found at

http:///lit/zip/slau319.

1.2Introduction

This bootstrap loader provides a method to program the flash memory during MSP430project

development and updates.It can be activated by a utility that sends commands via the UART protocol.

The BSL enables the user to control the activity of the MSP430and to exchange data using a personal computer or other device.

To avoid accidental overwriting of the BSL code,this code is stored in a secure memory location,either ROM or specially protected flash.To prevent unwanted source readout,any BSL command that directly or indirectly allows data reading is password protected.

To invoke the bootstrap loader,a BSL entry sequence must be applied to dedicated pins.After that,a

synchronization character,followed by the data frame of a specific command,initiates the desired

function.

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RST DTR /NMI

()

TEST

()RTS

RST DTR /NMI ()TEST ()RTS Standard RESET and BSL Entry Sequence http://

1.3Standard RESET and BSL Entry Sequence

1.3.1MSP430Devices With Shared JTAG Pins

Applying an appropriate entry sequence on the RST/NMI and TEST pins forces the MSP430to start

program execution at the BSL RESET vector instead of at the RESET vector located at address FFFEh.If the application interfaces with a computer UART,these two pins may be driven by the DTR and RTS signals of the serial communication port (RS232)after passing level shifters.Detailed descriptions of the hardware and related considerations can be found in Chapter 4.The normal user reset vector at FFFEh is used,if TEST is kept low while RST/NMI rises from low to high (standard method,see Figure 1-1).

Figure 1-1.Standard RESET Sequence

The BSL program execution starts when the TEST pin has received a minimum of two positive transitions and if TEST is high while RST/NMI rises from low to high (BSL entry method,see Figure 1-2).This level/transition triggering improves BSL startup reliability.

Figure 1-2.BSL Entry Sequence at Shared JTAG Pins

The TEST signal is normally used to switch the port pins P1.7to P1.4between their application function and the JTAG function.If the second rising edge at the TEST pin is applied while RST/NMI is still low,the TEST signal is kept low internally (application mode).

The BSL is not started via the BSL RESET vector if:

•There are fewer than two positive edges at the TEST pin while RST/NMI is low.

•TEST is low when RST/NMI rises from low to high.

•JTAG has control over the MSP430resources.

•Supply voltage,V CC ,drops below its threshold,and a power-on reset (POR)is executed.

•RST/NMI pin is configured for NMI functionality (NMI bit is set).

NOTE:The minimum timing for this sequence must be within the limits specified for the

corresponding pin in the data sheet.

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RST DTR /NMI

()

TCK ()RTS http:// UART Protocol

1.3.2MSP430Flash Devices With Dedicated JTAG Pins

Devices with dedicated JTAG pins use the TCK pin instead of the TEST pin.

The BSL program execution starts whenever the TCK pin has received a minimum of two negative

transitions and TCK is low while RST/NMI rises from low to high (BSL entry method,see Figure 1-3).This level/transition triggering improves BSL start-up reliability.

Figure 1-3.BSL Entry Sequence at Dedicated JTAG Pins

NOTE:The minimum timing for this sequence must be within the limits specified for the

corresponding pin in the data sheet.

The BSL is not started via the BSL RESET vector if

•There are fewer than two negative edges at TCK pin while RST/NMI is low.

•TCK is high if RST/NMI rises from low to high.

•JTAG has control over the MSP430resources.

•Supply voltage,V CC ,drops below its threshold,and a power-on reset (POR)is executed.

•RST/NMI pin is configured for NMI functionality (NMI bit is set).

1.3.3Devices With USB

Devices with USB are invoked when either of the following two conditions are met:

•The device is powered up by USB and the reset vector is blank.

•The device powers up with the PUR pin tied to V USB .

1.4UART Protocol

The UART protocol applied here is defined as:

•Baud rate is fixed to 9600baud in half-duplex mode (one sender at a time).

•Start bit,8data bits (LSB first),an even parity bit,1stop bit.

•Handshake is performed by an acknowledge character.

•Minimum time delay before sending new characters after characters have been received from the

MSP430BSL:1.2ms

NOTE:Applying baud rates other than 9600baud at initialization results in communication

problems or violates the flash memory write timing specification.The flash memory may be

extensively stressed or may react with unreliable program/erase operations.

1.5USB Protocol

The USB protocol applied here is defined as:

•HID protocol with one input endpoint and one output endpoint.Each endpoint has a length of 64bytes.•VID:0x2047

•PID:0x0200

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10Programming Via the Bootstrap Loader SLAU319A–July2010–Revised August2010

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Chapter2

SLAU319A–July2010–Revised August2010

ROM-Based Bootstrap Loader Protocol

2.1Synchronization Sequence

Before sending any command to the BSL,a synchronization character(SYNC)with its value of80h must be sent to the BSL.This character is necessary to calculate all the essential internal parameters,which maintain UART and flash memory program/erase timings.It provides the BSL system time reference.

Once this is received,an acknowledge DATA_ACK=90h is sent back by the BSL to confirm successful reception.

This sequence must be done before every command that is sent to the BSL.

NOTE:The synchronization character is not part of the Data Frame described in Section2.4.

2.2Commands

Two categories of commands are available:commands that require a password and commands that do not require a password.The password protection safeguards every command that potentially allows direct or indirect data access.

2.2.1Unprotected Commands

•Receive password

•Mass erase(erase entire flash memory,main as well as information memory)

•Transmit BSL version(V1.50or higher or in loadable BL_150S_14x.txt but not2.x BSLs)

•Change baud rate(V1.60or V1.61or V2.0x or in loadable BL_150S_14x.txt)

2.2.2Password Protected Commands

•Receive data block to program flash memory,RAM,or peripherals

•Transmit data block

•Erase segment

•Erase check(Present in V1.60or higher or in loadable BL_150S_14x.txt)

•Set Memory Offset(Present in V2.12or higher)

•Load program counter and start user program

•Change baud rate(BSL versions lower than V1.60and higher than2.10)

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Programming Flow http:// 2.3Programming Flow

The write access(RX data block command)to the flash memory/RAM or peripheral modules area is

executed online.That means a data byte/word is processed immediately after receipt and the write cycle is finished before a following byte/word has completely arrived.Therefore,the entire write time is

determined by the baud rate,and no buffering mechanism is necessary.

Data sections located below the flash memory area address are assumed to be loaded into the RAM or peripheral module area and,thus,no specific flash control bits are affected.

NOTE:If control over the UART protocol is lost,either by line faults or by violating the data frame

conventions,the only way to recover is to rerun the BSL entry sequence to initiate another

BSL session.

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http:// Data Frame 2.4Data Frame

To ensure high data security during the data transmission,a data frame protocol called serial standard protocol(SSP)is used.The BSL is considered the receiver in Table2-1.

2.4.1Data-Stream Structure

•The first eight bytes(HDR through LH)are mandatory(xx represents dummy data).

•Data bytes D1to Dn are optional.

•Two bytes(CKL and CKH)for checksum are mandatory.

•Acknowledge done by the BSL is mandatory,except with the TX data block and TX BSL version commands.

Table2-1.Data Frame of BSL Commands(1)(2)(3)(4)(5)(6)

Received

BSL HDR CMD L1L2AL AH LL LH D1D2…Dn CKL CKH ACK Command

RX data block8012n n AL AH n–40D1D2…Dn–4CKL CKH ACK RX password80102424xx xx xx xx D1D2…D20CKL CKH ACK Erase segment80160404AL AH02A5––––CKL CKH ACK Erase main or info80160404AL AH04A5––––CKL CKH ACK Mass erase80180404xx xx06A5––––CKL CKH ACK Erase check801C0404AL AH LL LH––––CKL CKH ACK Change baud rate80200404D1D2D3xx––––CKL CKH ACK Set mem offset80210404xx xx AL AH––––CKL CKH ACK Load PC801A0404AL AH xx xx––––CKL CKH ACK TX data block80140404AL AH n0––––CKL CKH–BSL responds80xx n n D1D2......…...…Dn CKL CKH–TX BSL version801E0404xx xx xx xx––––CKL CKH–BSL responds80xx1010D1D2......………D10CKL CKH–

(1)All numbers are bytes in hexadecimal notation.

(2)ACK is sent back by the BSL.

(3)The synchronization sequence is not part of the data frame.

(4)The erase check and TX BSL version commands are members of the standard command set in BSLs V1.50or higher but

excluding2.x BSLs.

(5)The change baud rate command is not a member of the standard command set(V1.60or higher or in loadable

BL_150S_14x.txt).

(6)Abbreviations

HDR:Header.Any value between80h and8Fh(normally80h).

CMD:Command identification

L1,L2:Number of bytes consisting of AL through Dn.Restrictions:L1=L2,L1<255,L1even

AL,AH:Block start address or erase(check)address or jump address LO/HI byte

LL,LH:Number of pure data bytes(250max)or erase information LO/HI byte or block length of erase check(FFFFh max)

D1…Dn:Data bytes

CKL,CKH:16-bit checksum LO/HI byte

xx:Can be any data

–:No character(data byte)received/transmitted

ACK:The acknowledge character returned by the BSL.Can be either DATA_ACK=90h:Frame was received correctly,

command was executed successfully,or DATA_NAK=A0h:Frame not valid(e.g.,wrong checksum,L1≠L2),command is not

defined,is not allowed,or was executed unsuccessfully.

n:Number of bytes consisting of AL through Dn

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Data Frame http:// 2.4.2Checksum

The16-bit(2bytes)checksum is calculated over all received/transmitted bytes B1...Bn in the data frame, except the checksum bytes themselves,by XORing words(two successive bytes)and inverting the result.

This means that B1is always the HDR byte and Bn is the last data byte just before the CKL byte.

Formula

CHECKSUM=INV[(B1+256×B2)XOR(B3+256×B4)XOR…XOR(Bn–1+256×Bn)]

or

CKL=INV[B1XOR B3XOR…XOR Bn–1]

CKH=INV[B2XOR B4XOR…XOR Bn]

2.4.3Example Sequence

The following example shows a request to read the memory of the MSP430from location0x0F00.All

values shown below are represented in hexadecimal format.

TO BSL:80

(Synchronization character sent to the BSL)

FROM BSL:90

(Acknowledge from BSL)

TO BSL:80140404F00F0E0085E0

(Send Command to read memory from0x0F00,length0x000E)

FROM BSL:80000E0E F213404000000000000002010101C0A2

(Returned values from BSL)

2.4.4Commands–Detailed Description

See Table2-1.

2.4.4.1General

Following the header byte HDR(80h)and the command identification CMD,the frame length bytes L1and L2(which must be equal)hold the number of bytes following L2,excluding the checksum bytes CKL and CKH.

Bytes AL,AH,LL,LH,D1...Dn are command-specific.However,the checksum bytes CKL(low byte)and CKH(high byte)are mandatory.

If the data frame has been received correctly and the command execution was successful,an

acknowledge character DATA_ACK=90h is sent back by the BSL.Incorrectly received data frames,

unsuccessful operations,and commands that are locked or not defined are confirmed with a DATA_NAK= A0h.

NOTE:BSL versions lower than V1.30support only byte-access operations.Therefore,the

peripheral module addresses at0100h to01FFh cannot be accessed correctly,because they

are word-oriented.In version V1.30and higher,addresses0000h to00FFh are accessed in

byte mode;all others are accessed in word mode.

2.4.4.2RX Data Block

The receive data block command is used for any write access to the flash memory/RAM or peripheral

module control registers at0000h to01FFh.It is password protected.

The16-bit even-numbered block start address is defined in AL(low byte)and AH(high byte).The16-bit even-numbered block length is defined in LL(low byte)and LH(high byte).Because pure data bytes are limited to a maximum of250,LH is always0.

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http:// Data Frame The following data bytes are succeeded by the checksum bytes CKL(low byte)and CKH(high byte).If the receipt and programming of the appropriate data block was successful,an acknowledge character

DATA_ACK is sent back by the BSL.Otherwise,the BSL confirms with a DATA_NAK.

NOTE:BSL versions V1.40and higher support online verification inside the MSP430for addresses

0200h to FFFFh,which reduces programming/verification time by50%.Online verification

means that the data is immediately verified with the data that is written into the flash without

transmitting it again.In case of an error,the loadable bootstrap loader BL_150S_14x.txt

additionally stores the first incorrectly written location address+3into the error address buffer

in the RAM at address0200h(021Eh for F14x devices).

2.4.4.3RX Password

The receive password command is used to unlock the password-protected commands,which perform

reading,writing,or segment-erasing memory access.It is not password protected.

Neither start address nor block length information is necessary,because the32-byte password is always located at addresses FFE0h to FFFFh.Data bytes D1to D20h hold the password information starting with D1at address FFE0h.

If the receipt and verification of the password is correct,a positive acknowledge DATA_ACK is sent back by the BSL,and the password-protected commands become unlocked.Otherwise the BSL confirms with a DATA_NAK.

Once the protected commands become unlocked,they remain unlocked until another BSL entry is

initiated.

2.4.4.4Mass Erase

The mass erase command erases the entire flash memory area(main memory plus information memory, see corresponding data sheet).It is not password protected.

All parameters shown in Table2-1are mandatory.After erasing,an acknowledge character DATA_ACK is sent back by the BSL.

Mass erase initializes the password area to32times0FFh.

NOTE:BSL versions V2.01and higher support automatic clearing of the LOCKA bit protecting

information flash memory.When the BSL is entered from a reset condition,LOCKA is

cleared by the BSL to mass erase the flash,including information memory.When the BSL is

entered in-application,user software should ensure that LOCKA is written as1prior to

initiating the BSL.Otherwise,information flash is not erased during a BSL mass erase.

2.4.4.5Erase Segment

The erase segment command erases specific flash memory segments.It is password protected.

The address bytes AL(low byte)and AH(high byte)select the appropriate segment.Any even-numbered address within the segment to be erased is valid.After segment erasing,an acknowledge character

DATA_ACK is sent back by the BSL(V1.40or lower).

BSL versions V1.60or higher perform a subsequent erase check of the corresponding segment and

respond with a DATA_NAK if the erasure was not successful.In this case,the first non-erased location address+1is stored in the error address buffer in the RAM at address0200h(021Eh for F14x devices).

In this version,a problem occurs if only one of the information memory segments is erased.In this case, an error is reported,because an automatic erase check over the whole information memory is performed.

As a solution,either erase the whole information memory or do a separate erase check after the erase, even if the erase reported an error.

Erase segment0clears the password area and,therefore,the remaining password is32times0FFh.

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Data Frame http:// When applying LL=0x04and LH=0xA5,a mass erasure of only the main memory is performed.Indeed, this command must be executed a minimum of12times to achieve a total erasure time of>200ms.No subsequent erase check of the entire main memory is http://e the erase check command additionally.

Check the device data sheet for more information on the cumulative(mass)erase time that must be met and the number of erase cycles required.

2.4.4.6Erase Main or Info

The erase main or info command erases specific flash memory section.It is password protected.

The address bytes AL(low byte)and AH(high byte)select the appropriate section of flash(Main or

INFO).Any even-numbered address within the section to be erased is valid.

2.4.4.7Erase Check

The erase check command verifies the erasure of flash memory within a certain address range.It is

password protected.

The16-bit block start address is defined in AL(low byte)and AH(high byte).The16-bit block length is defined in LL(low byte)and LH(high byte).Both can be either even or odd numbered to allow odd

boundary checking.

If the erase check of the appropriate data block was successful(all bytes contain0FFh),an acknowledge character DATA_ACK is sent back by the BSL.Otherwise,the BSL confirms with a DATA_NAK and the first non-erased location address+1is stored in the error address buffer at address0200h(021Eh for F14x devices).

NOTE:This command is not a member of the standard command set.It is implemented in BSL

version V1.60and higher or in the loadable bootstrap loader BL_150S_14x.txt.

2.4.4.8Change Baud Rate

The change baud rate command offers the capability of transmissions at higher baud rates than the

default9600baud.With faster data transition,shorter programming cycles can be achieved,which is

especially important with large flash memory devices.This command is not password protected.

Three control bytes(D1to D3)determine the selected baud rate.D1and D2set the processor frequency

(f≥f

min ),D3indirectly sets the flash timing generator frequency(f

FTGmin

≤f

FTG

≤f

FTGmax

).In detail:

D1:F1xx:Basic clock module control register DCOCTL(DCO.2to DCO.0)

F2xx:Basic clock module control register DCOCTL(DCO.2to DCO.0)

F4xx:FLL+system clock control register SCFI0(D,FN_8to FN_2)

D2:F1xx:basic clock module control register BCSCTL1(XT2Off,Rsel.2to Rsel.0)

F2xx:basic clock module control register BCSCTL1(XT2Off,Rsel.2to Rsel.0)

F4xx:FLL+system clock control register SCFI1(N

DCO

)

D30:9600Baud

1:19200Baud

2:38400Baud

After receiving the data frame,an acknowledge character DATA_ACK is sent back,and the BSL becomes prepared for the selected baud rate.It is recommended for the BSL communication program to wait

approximately10ms between baud rate alteration and succeeding data transmission to give the BSL

clock system time for stabilization.

NOTE:The highest achievable baud rate depends on various system and environment parameters

like supply voltage,temperature range,and minimum/maximum processor frequency.See

the corresponding device specification/data sheet.

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