Verilog程序12、VGA显示字符(6)

Verilog程序

else vga_rgb <= 8'b000_111_00;

10'd302: if(linea[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd303: if(lineb[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd304: if(linec[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd305: if(lined[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd306: if(linee[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00;

10'd307: if(linef[char_bit]) vga_rgb <= 8'b111_000_00;

else vga_rgb <= 8'b000_111_00; default: vga_rgb <= 8'hff;

endcase

end

else

vga_rgb <= 8'h000_000_11;

assign r = vga_rgb[7:5];

assign g = vga_rgb[4:2];

assign b = vga_rgb[1:0];

endmodule

本地地址：E:\FPGA\vedio\vga_char\src\i_vga_char.ucf

NET "clk" LOC = P54;

NET "rst_n" LOC = P38;

NET "hsync" LOC = P39;

NET "vsync" LOC = P35;

NET "r<2>" LOC = P70;