verilog_外部输入信号D触发器滤波

verilog_外部输入信号D触发器滤波

外部出入信号D触发器滤波

对于外部输出的信号，特别是按键类的比如旋转编码器等，在外部手动旋转的时候会输出的信号抖动很大，主要是在边沿的时候。

下面来介绍个多级D触发器滤除边沿抖动。不说废话直接上代码图片。

程序代码：

//----------触发时钟控制抖动滤除的时间--------------------

reg d_clk_a;

reg[15:0] counter_d_clk;

always@(posedge clk or negedge rst_n) begin

if(!rst_n) begin

counter_d_clk<=0;

d_clk_a<=0;

end

else if(counter_d_clk>=16'd500) begin

counter_d_clk<=0;

d_clk_a<=~d_clk_a;

end

else begin

counter_d_clk<=counter_d_clk+1'b1;

end

end

//------------3级D触发器去除抖动---------------------------

reg enter_ad0,enter_ad1,enter_ad2;

wire enter_ad;

reg enter_bd0,enter_bd1,enter_bd2;

wire enter_bd;

always@(posedge d_clk_a or negedge rst_n) begin

if(!rst_n)

enter_ad0<=0;

else

enter_ad0<=enter_a;

end

always@(posedge d_clk_a or negedge rst_n) begin

if(!rst_n)

enter_ad1<=0;

verilog_外部输入信号D触发器滤波

else

enter_ad1<=enter_ad0;

end

always@(posedge d_clk_a or negedge rst_n) begin if(!rst_n)

enter_ad2<=0;

else

enter_ad2<=enter_ad1;

end

assign enter_ad=enter_ad0&enter_ad1&enter_ad2; RLT图