数字逻辑设计及应用期末考试题(2010)

数字逻辑设计,数电

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二零零九至二零一零学年第 二 学期期 末 考试

考试日期年日

课程成绩构成：平时 20 分， 期中 20 分， 实验 0 分， 期末 60 分

一、To fill your answers in the blanks（1’×25）

1. If [X]10= - 110, then [X]two's-complement=[ 10010010 ]2,

[X]one's-complement=[ 10010001 ]2. (Assumed the number system is 8-bit long) 2. Performing the following number system conversions: A. [10101100]2=[ 000111010010 ]2421

B. [1625]10=[

0100100101011000 ]excess-3

10011000 ]8421BCD

C. [ 1010011 ]GRAY =[

3. If F A,B,C(1,2,3,6), then FD A,B,C( A,B,C(4. If the parameters of 74LS-series are defined as follows: VOLmax = 0.5 V, VOHmin = 2.7 V, VILmax = 0.8 V, VIHmin = 2.0 V, then the low-state DC noise margin is high-state DC noise margin is 5. Assigning 0 to Low and 1 to High is called positive logic. A CMOS XOR gate in positive logic is called gate in negative logic.

6. A sequential circuit whose output depends on the state alone is called a machine.

7. To design a "001010" serial sequence generator by shift registers, the shift register should need bit as least.

数字逻辑设计,数电

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8. If we use the simplest state assignment method for 130 sates, then we need at least state variables.

9. One state transition equation is Q*=JQ'+K'Q. If we use D flip-flop to complete the equation, 10. Which state in Fig. 1 is ambiguous

11.

Fig. 1 Fig. 2 12. If number [A]two's-complement =01101010 and [B]one's-complement =1001, calculate [A-B]two's-complement and indicate whether or not overflow occurs.(Assumed the number system is 8-bit long) [A-B]two's-complement overflow 13. If a RAM’s capacity is 16K words × 8 bits, the address inputs should be bits; We need 8 bits RAM to form a 16 K 32 bits ROM.. 14. Which is the XOR gate of the following circuit .

15. There are n－n invalid states in an n-bit ring counter state diagram. 16. An unused CMOS NOR input should be tied to logic level or . 17. The function of a DAC is translating the inputs to the same value of analog outputs.

二、Complete the following truth table of taking a vote by A,B,C, when more than two of A,B,C approve a resolution, the resolution is passed; at the same time, the resolution can’t go through if A don’t agree. For A,B,C, assume 1 is indicated approval, 0 is indicated opposition. For the F, assume 1 is passed, 0 is rejected.（5’）

数字逻辑设计,数电

三、The circuit to below realizes a combinational function F

of four variables. Fill in the Karnaugh map of the logic function F realized by the multiplexer-based circuit. (6’)

F=D∑(0,3,5,6)+D’∑(1,2,4,7)

四、(A) Minimize the logic function expression as follows

F = A·B + AC’ +B’·C+BC’+B’D+BD’+ADE(H+G) （5’）

F = A·B + AC’ +B’·C+BC’+B’D+BD’ = A·(B ’C)’ +B’·C+BC’+B’D+BD’

= A +B’·C+BC’+B’D+BD’+C’D (或= A +B’·C+BC’+B’D+BD’+CD’)

= A +B’·C+BD’+C’D (或= A + BC’+B’D+CD’)

数字逻辑设计,数电

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(B) To find the minimum sum of product for F and use NAND-NAND gates to realize it（6’）

F(W,X,Y,Z) Π(1,3,4,6,9,11,12,14)

F= X’Z’+XZ =( X’Z’+XZ)’’=(( X’Z’)’(XZ)’)’

五、Realize the logic function using one chip of 74LS139 and two NAND gates.（8’）

F(A,B,C) (2,6) G(C,D,E) (0,2,3) F(A,B,C)=C’∑(1,3) G(C,D,E)=C’∑(0,2,3)

六、Design a self-correcting modulo-6 counter with D flip-flops. Write out the excitation equations and output equation. Q2Q1Q0 denote the present states, Q2*Q1*Q0* denote the next states, Z denote the output. The state transition/output table is as following.（10’）

数字逻辑设计,数电

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激励方程式：D2=Q0’ （2分，错 -1分）

D1=Q2 （2分，错 -1分） D0=Q1 （2分，错 -1分）

修改自启动：D2=Q0 +Q2Q1’ （1分，错 -1分）

D1=Q2+Q1Q0’ （1分，错 -1分） D0=Q1+Q2Q0 （1分，错 -1分）

输出方程式：Z=Q1’Q0 （1分，错 -1分）

七、Construct a minimal state/output table for a moore sequential machine, that will detect the input sequences: x=101. If x=101 is detected, then Z=1.The input sequences DO NOT overlap one another. The states are denoted with S0~S3.（10’） For example:

X： 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 …… Z： 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 ……

state/output table

得 分

八、Please write out the state/output table and the transition/output table and the excitation/output table of this state machine.（states Q2 Q1=00~11, use the state name A~D）（10’）

数字逻辑设计,数电

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九、Clocked Synchronous State Machine Design（15’）

74x163 is a synchronous 4-bit binary counter with synchronous CLEAR input and LOAD

input. LD_L=(QBQC)', CLR_L=(QDQB )' in the following circuit. 1. Finish the logic circuit.

2. Draw the state diagram with all states of “Q3Q2Q1Q0” . (“Q3Q2Q1Q0” is the output of

数字逻辑设计,数电

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74x163)

3. Write the sequence of Y. Y is the output of 74x151. (Assumed state of 74x163 start in Q3Q2Q1Q0=0000.)

Y

CLOCK

(1) Finish the logic circuit. LD_L=(QBQC)', CLR_L=(QDQB )' (2) Q3Q2Q1Q0:

0000—0001—0010—0011—0100—0101—0110—1100—1101—1110—0000 (3) Y=0100111111