eda 时序逻辑电路实验报告(3)

实验程序：

LIDRART IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PAN4_5 IS

PORT(D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

y:OUT STD_LOGIC);

END PAN4_5;

ARCHITECTURE DEHA OF PAN4_5 IS

SIGNAL DATAIN:INTEGER;

BEGIN

DATA<=CONV_INTEGER(D);

PROCESS

BEGIN

IF(DATAIN>=5)THEN

Y<='1';

ELSE

Y<='0';

END PROCESS;

END DEHA;

编译结果