EDA与VHDL知识点总结与期末考试试卷及答案 (8)(7)

EDA与VHDL知识点总结与期末考试试卷及答案

End process;

End two;

Architecture three of mymux is

Begin

Cout <= ain and bin when sel = “00” else

Ain xor bin when sel = “01” else

Not ain when sel = “10” else not bin; End three;

六、根据原理图写出相应的VHDL程序：（10分）

Library ieee;

Use ieee.std_logic_1164.all;

Entity mycir is

Port ( A, B, clk : in std_logic;

Qout : out std_logic);

End mycir;

Architecture behave of mycir is

Signal ta, tb, tc;

Begin

tc <= ta nand tb;

Process (clk)

Begin

If clk’event and clk = ‘1’ then

Ta <= A;

Tb <= B;

End if;

End process;

Process (clk, tc)

Begin

If clk = ‘1’ then

Qout <= c;

End if;

End process;

End behave;