The simplescalar tool set, version 2.0(10)

under Contract DABT63-95-C-0127 and ARPA order no. D346. The current support for this work comes from a variety of sources, all of to which we are indebted.

tors to simulate multithreaded processors and multiprocessors. ASemantics:Linux port to SimpleScalar (enabling simulation of the OS on akernel with publicly available sources) is planned, using device-level emulation and a user-level le system. Other plans includeJR:

extending the tool set to simulate ISAs other than SimpleScalarOpcode:and MIPS (Alpha and SPARC ISA support will be the rst addi-Format:tions).

Semantics:As they stand now, these tools provide researchers with a sim-ulation infrastructure that is fast, exible, and ef cient. Changesin both the target hardware and software may be made with min-JALR:imal effort. We hope that you nd these tools useful, and encour-Opcode:age you to contact us with ways that we can improve the release,Format:Semantics:

documentation, and the tools themselves.

References

BEQ:

[1]

L.A. Belady. A Study of Replacement Algorithms for aOpcode:Virtual-Storage Computer.IBM Systems Journal, 5(2):78–Format:101, 1966.

Semantics:

[2]

Doug Burger, ToddM. Austin, and Steven Bennett. Evalu-ating Future Microprocessors: the SimpleScalar Tool Set.Technical Report 1308, Computer Sciences Department,University of Wisconsin, Madison, WI, July 1996.

BNE:

[3]

L.P. Horwitz, R.M. Karp, R.E. Miller, and A.Winograd.Opcode:Index Register Allocation.Journal of the ACM, 13(1):43–Format:61, January 1966.

Semantics:

[4]Charles Price.MIPS IV Instruction Set, revision 3.1. MIPSTechnologies, Inc., Mountain View, CA, January 1995.[5]

GurindarS. Sohi. Instruction Issue Logic for High-Perfor-mance, Interruptible, Multiple Functional Unit, PipelinedComputers.IEEE Transactions on Computers, 39(3):349–BLEZ:359, March 1990.

Opcode:[6]

RabinA. Sugumar and SantoshG. Abraham. Ef cientFormat:Semantics:

Simulation of Caches under Optimal Replacement withApplications to Miss Characterization. InProceedings ofthe 1993 ACM Sigmetrics Conference on Measurementsand Modeling of Computer Systems, pages 24–35, May1993.

BGTZ:Opcode:A Instruction set de nition

Format:Semantics:

This appendix lists all SimpleScalar instructions with theiropcode, assembler format, and semantics. The semantics areexpressed as a C-style expression that uses the extended opera-tors and operands described in Table3. Operands that are notBLTZ:listed in Table3 refer to actual instruction elds described inOpcode:Figure3. For each instruction, the next PC value (NPC) defaultsFormat:to the current PC value plus eight (CPC+8) unless otherwiseSemantics:

speci ed.

A.1 Control instructions

J:

Jump to absolute address.BGEZ:Opcode:0x01Opcode:Format:J target

Format:Semantics:SET_NPC((CPC & 0xf0000000) | (TARGET<<2)))

Semantics:

JAL:

Jump to absolute address and link.Opcode:0x02

Format:

JAL target

BC1F:SET_NPC((CPC\&0xf0000000) | (TARGET<<2))SET_GPR(31, CPC + 8))

Jump to register address.0x03JR rs

TALIGN(GPR(RS))SET_NPC(GPR(RS))

Jump to register address and link.0x04JALR rs

TALIGN(GPR(RS))

SET_GPR(RD, CPC + 8)

SET_NPC(GPR(RS))

Branch if equal.0x05

BEQ rs,rt,offset

if (GPR(RS) == GPR(RT))

SET_NPC(CPC + 8 + (OFFSET << 2))else

SET_NPC(CPC + 8)

Branch if not equal.0x06

BEQ rs,rt,offset

if (GPR(RS) != GPR(RT))

SET_NPC(CPC + 8 + (OFFSET << 2))else

SET_NPC(CPC + 8)

Branch if less than or equal to zero.0x07

BLEZ rs,offset

if (GPR(RS) <= 0)

SET_NPC(CPC + 8 + (OFFSET << 2))else

SET_NPC(CPC + 8)

Branch if greater than zero.0x08

BGTZ rs,offset

if (GPR(RS) > 0)

SET_NPC(CPC + 8 + (OFFSET << 2))else

SET_NPC(CPC + 8)

Branch if less than zero.0x09

BLTZ rs,offset

if (GPR(RS) < 0)

SET_NPC(CPC + 8 + (OFFSET << 2))else

SET_NPC(CPC + 8)

Branch if greater than or equal to zero.0x0a

BGEZ rs,offset

if (GPR(RS) >= 0)

SET_NPC(CPC + 8 + (OFFSET << 2))else

SET_NPC(CPC + 8)

Branch on oating point compare false.