The simplescalar tool set, version 2.0(12)

under Contract DABT63-95-C-0127 and ARPA order no. D346. The current support for this work comes from a variety of sources, all of to which we are indebted.

WRITE_WORD(GPR(RT+1), GPR(RS)+OFF-SET+4)

Format:Semantics:

DSW:

Opcode:Format:Double store word, indexed addressing.0xd0

DSW rt,(rs+rd) inc_dec

SWR rt,offset(rs)

Seess.def for a detailed description of thisinstruction’s semantics. NOTE: SWR does notsupport pre-/post- inc/dec.

A.3 Integer instructions

Semantics:

DSZ:

Opcode:Format:Semantics:DSZ:

Opcode:Format:Semantics:S.S:

Opcode:Format:Semantics:S.S:

Opcode:Format:Semantics:S.D:Opcode:Format:Semantics:

S.D:Opcode:Format:Semantics:

SWL:

Opcode:Format:Semantics:

SWR:

Opcode:

WRITE_WORD(GPR(RT), GPR(RS)+GPR(RD))WRITE_WORD(GPR(RT+1),ADD:

GPR(RS)+GPR(RD)+4)

Opcode:Double store zero, displaced addressing.Format:Semantics:0x38

DSW rt,offset(rs) inc_dec

WRITE_WORD(0, GPR(RS)+OFFSET)ADDI:WRITE_WORD(0, GPR(RS)+OFFSET+4)

check).Double store zero, indexed addressing.Opcode:0xd1

Format:DSW rt,(rs+rd) inc_dec

Semantics:WRITE_WORD(0, GPR(RS)+GPR(RD))WRITE_WORD(0, GPR(RS)+GPR(RD)+4)

ADDU:Store word from oating point register le,Opcode:displaced addressing.Format:Semantics:0x36

S.S ft,offset(rs) inc_dec

ADDIU:WRITE_WORD(FPR_L(FT), GPR(RS)+OFF-SET)

check).Opcode:Store word from oating point register le,Format:indexed addressing.Semantics:0xc9

S.S ft,(rs+rd) inc_dec

SUB:

WRITE_WORD(FPR_L(FT),Opcode:GPR(RS)+GPR(RD))

Format:Semantics:Store double word from oating point regis-ter le, displaced addressing.SUBU:0x37

check).S.D ft,offset(rs) inc_dec

Opcode:WRITE_WORD(FPR_L(FT), GPR(RS)+OFF-Format:SET)

WRITE_WORD(FPR_L(FT+1), GPR(RS)+OFF-Semantics:SET+4)

MULT:Store double word from oating point regis-Opcode:ter le, indexed addressing.Format:0xd2

Semantics:S.D ft,(rs+rd) inc_dec

WRITE_WORD(FPR_L(FT),GPR(RS)+GPR(RD))

MULTU:WRITE_WORD(FPR_L(FT+1),Opcode:GPR(RS)+GPR(RD)+4)

Format:Semantics:

Store word left, displaced addressing.0x39

SWL rt,offset(rs)

Seess.deffor a detailed description of thisDIV:

instruction’s semantics. NOTE: SWL does notOpcode:support pre-/post- inc/dec.

Format:Semantics:

Store word right, displaced addressing.0x3a

Add signed (with over ow check).0x40

ADD rd,rs,rt

OVER(GPR(RT),GPR(RT))

SET_GPR(RD, GPR(RS) + GPR(RT))

Add immediate signed (with over ow0x41

ADDI rd,rs,rt

OVER(GPR(RS),IMM)

SET_GPR(RT, GPR(RS) + IMM)

Add unsigned (no over ow check).0x42

ADDU rd,rs,rt

SET_GPR(RD, GPR(RS) + GPR(RT))

Add immediate unsigned (no over ow0x43

ADDIU rd,rs,rt

SET_GPR(RT, GPR(RS) + IMM)

Subtract signed (with under ow check).0x44

SUB rd,rs,rt

UNDER(GPR(RS),GPR(RT))

SET_GPR(RD, GPR(RS) - GPR(RT))

Subtract unsigned (without under ow0x45

SUBU rd,rs,rt

SET_GPR(RD, GPR(RS) - GPR(RT))

Multiply signed.0x46

MULT rs,rt

SET_HI((RS * RT) / (1<<32))SET_LO((RS * RT) % (1<<32))

Multiply unsigned.0x47

MULTU rs,rt

SET_HI(((unsigned)RS * (unsigned)RT)/(1<<32))SET_LO(((unsigned)RS*(unsigned)RT) %(1<<32))

Divide signed.0x48DIV rs,rt

DIV0(GPR(RT))

SET_LO(GPR(RS) / GPR(RT))SET_HI(GPR(RS) % GPR(RT))