MEMORY存储芯片MT29F256G08AUCABH3-10A中文规格书

Asynchronous Interface Bus Operation

The bus on the device is multiplexed. Data I/O, addresses, and commands all share the

same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and

commands are always supplied on I/O[7:0].

The command sequence typically consists of a COMMAND LATCH cycle, address input

cycles, and one or more data cycles, either READ or WRITE.

Table 4: Asynchronous Interface Mode Selection

Notes: 1.Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V IH

or V IL.

2.WP# should be biased to CMOS LOW or HIGH for standby.

Asynchronous Enable/Standby

When the device is not performing an operation, the CE# pin is typically driven HIGH

and the device enters standby mode. The memory will enter standby if CE# goes HIGH

while data is being transferred and the device is not busy. This helps reduce power con-

sumption.

The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-

chronous memory bus as other Flash or SRAM devices. Other devices on the memory

bus can then be accessed while the NAND Flash is busy with internal operations. This

capability is important for designs that require multiple NAND Flash devices on the

same bus.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal

signifies that an ADDRESS INPUT cycle is occurring.

Asynchronous Commands

An asynchronous command is written from I/O[7:0] to the command register on the ris-

ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.

Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some

commands, including READ STATUS (70h), are accepted by die (LUNs) even when they

are busy.

For devices with a x16 interface, I/O[15:8] must be written with zeros when a command

is issued.

PDF: 09005aef83e5ffed

m68a_1gb_nand.pdf - Rev. L 10/12 EN