MEMORY存储芯片MT29F256G08AUCABH3-10A中文规格书(4)

Status Operations

Each die (LUN) provides its status independently of other die (LUNs) on the same target through its 8-bit status register.

After the READ STATUS (70h) command is issued, status register output is enabled. The contents of the status register are returned on I/O[7:0] for each data output request.When the asynchronous interface is active and status register output is enabled,

changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is not necessary to toggle RE# to see the status register update.

While monitoring the status register to determine when a data transfer from the Flash array to the data register (t R) is complete, the host must issue the READ MODE (00h)command to disable the status register and enable data output (see Read Operations).With internal ECC enabled, a READ STATUS command is required after completion of the data transfer (t R_ECC) to determine whether an uncorrectable read error occurred.

Table 14: Status Register Definition

Notes:

1.Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.

2.Status register bit 5 is 0 during the actual programming operation. If cache mode is

used, this bit will be 1 when all internal operations are complete.

3. A status register bit defined as Rewrite Recommended signifies that the page includes

acertain number of READ errors per sector (512B (main) + 4B (spare) + 8B (parity). A re-writeof this page is recommended. (Up to a 4-bit error has been corrected if internal ECC was enabled.)

4. A status register bit defined as FAIL signifies that an uncorrectable READ error has oc-curred.

1Gb x8, x16: NAND Flash Memory

Status Operations

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m68a_1gb_nand.pdf - Rev. L 10/12 EN