MEMORY存储芯片MT29F256G08AUCABH3-10A中文规格书(5)

Column Address Operations

The column address operations affect how data is input to and output from the cache

registers within the selected die (LUNs). These features provide host flexibility for man-

aging data, especially when the host internal buffer is smaller than the number of data

bytes or words in the cache register.

When the asynchronous interface is active, column address operations can address any

byte in the selected cache register.

RANDOM DATA READ (05h-E0h)

The RANDOM DATA READ (05h-E0h) command changes the column address of the se-

lected cache register and enables data output from the last selected die (LUN). This

command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It

is also accepted by the selected die (LUN) during CACHE READ operations

(RDY = 1; ARDY = 0).

Writing 05h to the command register, followed by two column address cycles containing

the column address, followed by the E0h command, puts the selected die (LUN) into

data output mode. After the E0h command cycle is issued, the host must wait at least

t WHR before requesting data output. The selected die (LUN) stays in data output mode

until another valid command is issued.

Figure 31: RANDOM DATA READ (05h-E0h) Operation

Cycle type

I/O[7:0]

SR[6]

1Gb x8, x16: NAND Flash Memory Column Address Operations

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m68a_1gb_nand.pdf - Rev. L 10/12 EN