SPI_Layout_Guide_AN(2)

针对高速SPI FLASH的PCB走线规则。

Application

Note

Figure 2.2 Simplified Connection Diagrams for S70FL Single and Multi I/O Configurations

Often multiple SPI devices are connected to a single host. Figure2.3 illustrates such a configuration. Use of a dual die S70FL device can be viewed as use of Device 1 and Device 2 in Figure2.3.

Figure 2.3 Simplified Multi- SPI Device Connection Diagram

Many SPI flash applications do not utilize the ACC, WP# or HOLD# functions. In those applications where an input is not utilized, the unused I/O should be pulled up to VCC, or VIO if present, via a suitable resistor, e.g. 4.7 to 10 kohms.

针对高速SPI FLASH的PCB走线规则。

Application

Note

3.SPI Flash Packaging

The FL-P and FL-S SPI Flash families provide a user configurable high speed single, dual or quad channel interface to the host controller. Spansion SPI flash are available in a variety of packages, including SOIC-8 and SOIC-16 leaded packages, USON-8 and WSON-8 leadless packages and FAB024 and FAC024 ball grid array (BGA) packages. Table3.1 provides a matrix of package options for all FL-P and FL-S devices.

Table 3.1 Device Availability Matrix

Package \ DensitySOC008SO3 016

32 MbitS25FL032PS25FL032P

64 Mbit

S25FL064P

128 Mbit

S25FL128P S25FL129P S25FL128S

256 Mbit

S25FL256S

512 Mbit

S25FL512S

1024 Mbit

SL3S70FL256PUSONWSON

S25FL0

32PS25FL032P

S25FL064P

S25FL128P

S25FL129P S25FL128SS25FL129P S25FL128SS25FL129P S25FL128S

S25FL256S

FAB024FAC024ZSA024other BGA (planned)

S25FL032PS25FL032P

S25FL064PS25FL064P

S25FL256SS25FL256S

S25FL512S S70FL512S

S70FL01GS

S70FL256P

3.1SPI Flash Package Connection Diagrams

Applicable package connection diagrams are provided in each SPI Flash data sheet. These diagrams are

included here in Figure3.1 through Figure3.11 for reference.

Figure 3.1 SOC 008 wide – S25FL032P