SPI_Layout_Guide_AN(9)

针对高速SPI FLASH的PCB走线规则。

Application

Note

Figure 5.1 Routing with Decoupling Capacitor

5.2Clock Signal Routing

For reliable high speed synchronous data transfers, it is essential for the clock signal to have very good signal

integrity. The following recommendations should be taken into consideration when routing the clock signal. Run the clock signal at least 3x of the trace width away from all other signal traces. This will help keep clock signal clean from noise, reference Figure5.2. Use as few vias as possible for the entire path of the clock signal. Each via will create impedance changes and signal reflections. Run the clock trace as straight as possible and avoid using serpentine routing, reference Figure5.3. Keep a continuous ground in the next layer as a reference plane.

Route the clock trace with controlled impedance, typically a 50 ohm trace impedance with ± 5% tolerance.

Figure 5.2 Separate Clock from other Traces

针对高速SPI FLASH的PCB走线规则。

Application

Note

Figure 5.3 Straight Trace Runs for Clock

5.3Data Signal Routing

The FL Flash support 1, 2 and 4-bit data bus configurations. In 2 and 4-bit multiple I/O configurations, it is

important that the I/O traces are routed such that they have identical lengths, within ~ 3 mm, to assure

equivalent propagation delays. To assure reliable data transfers for all configurations it is important that the propagation delays for the clock trace and all data traces are identical.

The data signals should be routed with traces of controlled impedance to reduce signal reflection. Data traces should have no 90° angle corners. The preferred method for implementing a 90° angle change is to cut the corner to smooth the trace, reference Figure5.4. To maximize signal integrity, avoid using multiple signal layers for data signal routing and ensure all signal traces have a continuous reference plane.

Figure 5.4 Signal Routing at the Corner

5.4Via Routing

Vias should not be placed within a land pad as this can cause solder wicking inside the via hole, resulting in

misshapen solder joints and electrical opens. Vias should be placed a minimum of 0.3 mm away from the solder pad as shown in Figure5.5

.