ABSTRACT Leakage Power Modeling and Optimization in Intercon(2)

Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 95-98 % accuracy agains

Sotoderiveanarchitecturalleakagepowermodel,we

cantransistorseparateprocesstechnology:

widththefromtechnology-independentthosethatstayinvariantvariablesforasuchspeci casIleak(i,s)=

W(type(i,s))L

·I

leak(i,s)

(3)

whereIleakagecurrent.I

leakistotalleakisleakagecur-rentperunittransistorwidthoverlength.W(type(i,s))referstothetransistorwidthofNMOSwhenNMOSdeter-minestheleakagecurrent(i.e.type(i,s)isN),orPMOS(whentype(i,s)isP).Astransistorwidthhasanegligi-blee ectonI

leak(i,s),Ileak(i,s)is xedforagivencircuittypeandinputstateundercertaintechnologyandature.Withthisapproximation,armedwithI

temper-leakforvar-iouskindsofcircuitcomponentsatdi erentinputstates,architectscanestimatetheleakagepowerforarchitecturalunitscomposedfromthesecircuitcomponents.Ourpro-posedmodelingmethodologyisasfollows:

1.Identifythefundamentalcircuitcomponents,andde-riveI

leak(i,s)foreachatdi erentinputstates.Exam-plesaresingleNMOSandPMOStransistors,NANDgates,inverters,etc.2.De nemajorarchitecturalbuildingblocks.Forinter-connectionnetworks,typicalbuildingblockswillbebu ers,crossbars,arbitersandlinks[9].Formicro-processors,suitablebuildingblockswillbecachelines,adders,etc.3.Identifythedistributionoftheinputstatesbasedonoperationcharacteristicsorsimulationandderivear-chitecturalequationsthatestimatetheleakagepowerforeachbuildingblock.Webelievethisisthe rstleakagepowermodelingmethod-ologythattrulyseparatestechnology-dependentandinde-pendentvariables.In[2],asinglekdesignisusedtore ectthecompositionofdevicetypes(N/P),geometries(W/L),states(on/o ),andstackingfactors.Asaresult,kdesignisextremelysensitivetochangesinanyofthevariablesandtheimpactofarchitecturalparametershardtoisolate.In

[6],Pleaklib

=χlib·CellsSlib

isusedtoestimatetheleak-agepowerinanASICdesignenvironment,whereχlib,Slibaretechnology-dependentparametersderivedthroughex-perimentsand”Cells”isthenumberofcellsinthedesign.Thismodeltargetsalaterdesignstagethenthearchitec-turalstage,whendesignersexplorevariouscircuitdesignsforaselectedarchitecture.

2.1DerivationofI

leak

Foreachcomponenti,wesimulateI

leak(i,s)usingHSPICEandtheBerkeleyPredictiveTechnologyModel[1]fortherangeofprocesstechnologiesandassociatedparametersinTable1.Table2liststheI

listed

leak(i,s)simulatedforeachfun-damentalcircuitcomponenti(Leakagecurrentsdi ersatdi erentstatesduetostakingandbodybiase ects).Cir-cuitstructurescanthenbehierarchicallycomposedfromthesefundamentalcircuitcomponents.

Table1:Parametersforvarioustechnologies.

th0dd

Table2:Ileak(i,s)foreachfundamentalcircuitcompo-

nentiatdi erentinputstatessattemperature80oC.Type(i,s)indicatesiftheNMOSorPMOStransistorisdominantindeterminingleakagecurrent.

I(i,s)

i

s(i,s)1P4.0e-99.7e-980.4e-901N7.9e-910.8e-946.0e-910N4.7e-95.1e-944.0e-911P8.1e-919.4e-9159.5e-901P3.6e-95.9e-945.3e-910P4.3e-99.7e-977.5e-911

P

0.9e-90.7e-9

5.9e-9

Figure1:AFIFObu erwith1readportand1write

port(adaptedfrom[4]).Tcisthepre-chargingtransis-tor,Twdthewordlinedriver,Tbdthewritebitlinedriver,Tmthememorycellinverter,andTprandTpwthepasstransistorsconnectingreadandwriteportstomemorycellsrespectively.

2.2Leakagepowermodelingofrouterbuffers

Weappliedourmethodologytothemajorbuildingblocksofinterconnectionnetworksasidenti edin[9]–bu ers,crossbars,arbiters,andlinks.Here,wewalkthroughourmodelingofrouterbu erstodemonstratethemethodology.Fig.1sketchesthecircuitstructureofarouterbu erpoolwithB it1bu ers,eachFbitswide,withPrreadportsandPwwriteports.ItshowsaFIFObu erthatiscomposedofthefundamentalcircuitcomponentsofPMOS,NMOStransistorsandinverters.Dimensionsofthecircuitstruc-turesuchashcell,wcell,dwareestimatedbyOrion[9]fromarchitecturalparameters.

Inputstateprobabilisticanalysis.Next,weanalyzetheprobabilitydistributionofeachinputstateofacircuitcomponentbyexamininghowarchitecturalunitsfunction.Forinstance,thewordlineinverterTwdisset(s=0)wheneverthatbu er/rowisreadorwritten.Thus,atanypointintime,onlyoneoutofBwordlineinverterswillbe

set.Hence,Ileak(Twd)=1W(type(INV,0))

·I leak(INV,0)+B 1W(type(INV,1)) ·Ileak(INV,1).Basically,giventheseI

leak(i,s),andtheprobabilitiesof1

segmentA itisofshortapacket.

for owcontrolunit,andisa xed-length