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ABSTRACT Leakage Power Modeling and Optimization in Intercon(6)

发布时间:2021-06-07   来源:未知    
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Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 95-98 % accuracy agains

Figure6:LeakagepowersavingsunderLookahead-Singlepolicyfor64- itbu er.

networkarchitectures.

Bydelineatingthedesignspaceforpower-awarebu erpolicies,andexploringtheimpactofseveralsimplealterna-tives,wehopeourworkwillmotivatetheproposalofso-phisticatedpoliciesinthefuture.

Acknowledgments

TheauthorsaregratefultoK.FlautnerofUniversityofMichiganandS.KimofCarnegieMellonforprovidingde-tailedparametersofDrowsyCacheandGatedVddrespec-tively.AtPrinceton,wewishtothankHang-ShengWangforhishelpincharacterizingdynamicpowerusingOrion

Figure7:

LeakagepowersavingsunderLookahead-AggressiveandPredictivepoliciesfor64- itbu er.

Figure8:Averagelatencyunderdi erentpoliciesfor

GatedVddSRAMs.

andLiShangforassistancewiththePopNetnetworksimu-lator.ThisworkispartiallyfundedbyNSFCAREERgrantCCR-0237540.

7.REFERENCES

[1]BerkeleyPredictiveTechnologyModelandBSIM4.

Availableat

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[3]W.J.DallyandB.Towles.“Routepackets,notwires:

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[4]K.Flautner,N.S.Kim,S.Martin,D.Blaauw,andT.

Mudge,“Drowsycaches:simpletechniquesforreducingleakagepower”,puterArchitecture,Alaska,May2002,pp.219-230.

[5]http://www.ee.princeton.edu/~lshang/popnet.html

[6]R.Kumar,C.P.Ravikumar,“Leakagepowerestimation

fordeepsubmicroncircuitsinanASICdesigninvironment”,InProc.ASP-DAC/VLSIDesign,Bangalore,India,2002.pp.45-50.

[7]M.Powell,S.-H.Yang,B.Falsa ,K.Roy,andT.N.

Vijaykumar,“Gated-Vdd:acircuittechniquetoreduceleakageindeep-submicroncachememories”,InProc.Intl.Symp.LowPowerElectronicsandDesign,Italy,July,2000,pp.90-95.

[8]L.Shang,L.-S.Peh,andN.K.Jha,“Dynamicvoltage

scalingwithlinksforpoweroptimizationofinterconnectionnetworks”,InProc.Intl.Symp.onHigh-PerformanceComputerArchitecture,California,Jan.2003,pp.79-90.[9]H.Wang,X.Zhu,L.-S.Peh,andS.Malik,“Orion:a

power-performancesimulatorforinterconnectionnetworks”,InProc.Intl.Symp.Microarchitecture,Istanbul,Turkey,Nov.2002,pp.294-305.

[http://www.ee.princeton.edu/~peh/orion.html]

[10]F.Worm,P.Ienne,P.ThiranandG.D.Micheli,“An

adaptivelowpowertransmissionschemeforon-chip

networks”,InProc.Intl.Symp.SystemsSynthesis,Kyoto,Japan,October2002,pp.92-100.

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