ABSTRACT Leakage Power Modeling and Optimization in Intercon(3)

Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 95-98 % accuracy agains

eachblockinputstatePI=

rob (i,s),theleakagecurrentforabuilding

Prob(i,s)

W(type(i,s))leakis:

(Block)·I leak(i,s)(4)

i

s

L

whereW(type(s))referstothetransistorwidthofNMOS(when

type(s)isN)orPMOS(whentype(s)isP).

throughInputnetworkstatesimulation.simulation.

InputstatescanalsobetrackedIleak(Block,t)=

W(type(i,s(t)))L·I

leak(i,s(t))

(5)

i

where,Ileak(Block,t)istheleakagecurrentattimet,and

s(t)isthestateofcircuittypeiattimetwithinthiscircuitblock.

Finally,wecanestimatethetotalleakagecurrentofarouterbu er(Eq.6)whileitsleakagepowerisleakagecur-rentmultipliedbysupplyvoltage(Eq.7).

Ileak(buffer)=(Pr+Pw)BIleak(Twd)+2PwFIleak(Tbd)+2BFIleak(Tc)+2BFIleak(Tm)

+2BF(PwIleak(Tpw)+Pr·Ileak(Tpr))

(6)Pleak(buffer)=Ileak(buffer)·Vdd

(7)

2.3Validation

WevalidatedourmodelwithHSPICEsimulationofeachcompletefunctionalunitofachip-to-chiprouter(crossbar,arbiter,andbu ers)in0.07µmtechnology.Leakagecur-rentsunderdi erentinputstateswereestimatedwithourmodelandcomparedwiththeleakagecurrentsobtainedfromHSPICEsimulationforthesamefunctionalunitwiththesameinputstates,theexactstructureandfeaturesizes.Forinstance,a5-by-5matrixcrossbarunithas5datain-putsand25controlsignals.Thecombinationoftheirvaluesdeterminetheinputstateofthecrossbarandthustheleak-agecurrent.Forsuchfunctionalunitswithavastnumberofpossibleinputstates,weselectarandomsampleoftyp-icalinputstatesforvalidation.Theaccuracyofourmodelforthesefunctionalunitsiscomputedbyaveragingacrossdi erentinputstates.Table3showsmeanandstandardde-viationofourmodel’serrorin0.07µmtechnologycomparedwithHSPICEsimulation.Sinceleakagecurrentislargeat0.07µm,weexpectthemagnitudeoferrortobelargerthanthatinearlierprocesstechnology.

Table3:Validationofourmodelvs.HSPICEsimula-tionforeachmajorbuildingblockofarouter.

3.

DYNAMICANDLEAKAGEPOWERCH-ARACTERIZATIONOFINTERCONNE-CTIONNETWORKS

CombinedwithOrion,anarchitecturaldynamicpowermodelfornetworks[9],wecharacterizedthetotalpowerconsumptionofbothanon-chipnetworkandachip-to-chip

network.Theon-chipnetworkisparameterizedasin[3],witha4-by-4meshnetworkona12mm2chip,eachnodeclockedat1GHz,with5input/outputports(oneofwhichistheinjection/ejectionport),64 itbu ersperinputport(each it128bitswide),connectedwitha5-by-5matrixcrossbarand55:1arbiters.Therouterinthechip-to-chipnetworkhas256128-bit itbu ersperinputportinstead,otherparametersremainingthesameasthatintheon-chipnetwork.ThefeaturesizeofthetransistorsisderivedbyOrion[9]fromarchitecturalparametersbasedonthetimingdelayrequirementsandassumingminimumarea.

E ectofprocesstechnology.Tables4and5showtheestimatesforarouterinachip-to-chipandon-chipnetworkrespectivelyat50% itarrivingratein1sat80oC.Astech-nologyscales,leakagepowerbecomesincreasinglysigni -cant,startingfrom2.5%oftotal(leakage+switching)poweratcurrent0.18µmtechnology,toahefty60%at0.07µmtechnologyifclockfrequencyiskeptinvariantforthechip-to-chipnetwork.Evenassumingdoublingclockfrequenciesaswescaleprocesstechnology,leakagepowerremainsasig-ni cant27%at0.07µm.Thoughtheon-chipnetworkhasfewerstorageelements,leakagepowerstillrisestoasigni -cant21%at0.07µm,assumingclockfrequencydoubleseachprocessgeneration.

Table4:Dynamicandleakagepowerestimatesofa

routerinachip-to-chipnetwork.

power(W)power(W)Distributionofleakagepowerbetweenrouterandlinks.FromTable5,itisevidentthatfull-swingon-chiplinkdriversandwiresconsumesubstantialdynamicpower,overwhelmingthatoftheroutercorein0.10and0.07µmpro-cesses.However,whenyoulookatleakagepowerconsump-tionofroutervs.links,theconverseistrue.Aswiresdonotdissipateleakagepower,theleakagepowerconsumptionofjustthedriversisminimal,comparedtothatoftheroutercore.Thispromptedustodelveintoaleakagepowerbreak-downofvariousfunctionalunitswithinanon-chiprouter.Breakdownofleakagepowerwithinarouter.Fig.2showstheleakagepowerconsumedbythevariousmajorfunctionalunitsofanon-chiprouteranditslinksatdif-ferentprocesstechnologies.Itshowsbu ersconsumingap-proximately64%percentleakagepowerofthetotalnode(router+link)forallprocesstechnologies,standingasthelargestleakagepowerconsumer.Ourcharacterizationhigh-lightsrouterbu ersasaprimecandidateforleakagepoweroptimization.

4.POWER-AWAREBUFFERS

Asinterconnectionnetworksexperiencesigni canttem-poralandspatialvarianceinworkloadthatleadstohighlyvaryingbu erutilization,weproposepower-awarebu ersasanarchitecturaltechniqueforleakagepoweroptimizationininterconnectionnetworks–i.e.bu ersthatregulatetheirownleakagepowerconsumptionbasedonactualutilization.