FPGA实现双向IO口与时钟芯片的例子(4)

module ds1302_module

(

CLK, RSTn,

Start_Sig,

Done_Sig,

Time_Write_Data,

Time_Read_Data,

RST,

SCLK,

SIO

);

input CLK;

input RSTn;

input [7:0]Start_Sig;

output Done_Sig;

input [7:0]Time_Write_Data;

output [7:0]Time_Read_Data;

output RST;

output SCLK;

inout SIO;

wire [7:0]Words_Addr;

wire [7:0]Write_Data;