FPGA实现双向IO口与时钟芯片的例子(7)

output [7:0]Time_Read_Data;

input Access_Done_Sig;

output [1:0]Access_Start_Sig;

input [7:0]Read_Data;

output [7:0]Words_Addr;

output [7:0]Write_Data;

reg [7:0]rAddr;

reg [7:0]rData;

always @ ( posedge CLK or negedge RSTn )

if( !RSTn )

begin

rAddr <= 8'd0;

rData <= 8'd0;

end

else

case( Start_Sig[7:0] )

8'b1000_0000 : // Write unprotect begin rAddr <= { 2'b10, 5'd7, 1'b0 }; rData <= 8'h00; end

8'b0100_0000 : // Write hour

begin rAddr <= { 2'b10, 5'd2, 1'b0 }; rData <= Time_Write_Data; end

8'b0010_0000 : // Write minit begin rAddr <= { 2'b10, 5'd1, 1'b0 }; rData <= Time_Write_Data; end

8'b0001_0000 : // Write second