FPGA实现双向IO口与时钟芯片的例子(8)

begin rAddr <= { 2'b10, 5'd0, 1'b0 }; rData <= Time_Write_Data; end

8'b0000_1000 : // Write protect begin rAddr <= { 2'b10, 5'd7, 1'b0 }; rData <= 8'b1000_0000; end

8'b0000_0100 : // Read hour begin rAddr <= { 2'b10, 5'd2, 1'b1 }; end

8'b0000_0010 : // Read minit begin rAddr <= { 2'b10, 5'd1, 1'b1 }; end

8'b0000_0001 : // Read second begin rAddr <= { 2'b10, 5'd0, 1'b1 }; end

endcase

reg [1:0]i;

reg [7:0]rRead;

reg [1:0]isStart;

reg isDone;

always @ ( posedge CLK or negedge RSTn )

if( !RSTn )

begin

i <= 2'd0;

rRead <= 8'd0;

isStart <= 2'b00;

isDone <= 1'b0;

end