FPGA实现双向IO口与时钟芯片的例子(5)

wire [1:0]Access_Start_Sig;

cmd_control_module U1

(

.CLK( CLK ),

.RSTn( RSTn ),

.Start_Sig( Start_Sig ), // input - from top

.Done_Sig( Done_Sig ), // output - to top

.Time_Write_Data( Time_Write_Data ), // input - from top .Time_Read_Data( Time_Read_Data ), // output - to top .Access_Done_Sig( Access_Done_Sig ), // input - from U2 .Access_Start_Sig( Access_Start_Sig ), // output - to U2 .Read_Data( Read_Data ), // input - from U2 .Words_Addr( Words_Addr ), // output - to U2

.Write_Data( Write_Data ) // output - to U2

);

wire [7:0]Read_Data;

wire Access_Done_Sig;

function_module U2

(

.CLK( CLK ),

.RSTn( RSTn ),

.Start_Sig( Access_Start_Sig ), // input - from U1 .Words_Addr( Words_Addr ), // input - from U1

.Write_Data( Write_Data ), // input - from U1

.Read_Data( Read_Data ), // output - to U1

.Done_Sig( Access_Done_Sig ), // output - to U1

.RST( RST ), // output - to top

.SCLK( SCLK ), // output - to top

.SIO( SIO ) // output - to top

);