FPGA实现双向IO口与时钟芯片的例子(6)

Endmodule

module cmd_control_module

(

CLK, RSTn,

Start_Sig,

Done_Sig,

Time_Write_Data,

Time_Read_Data,

Access_Done_Sig,

Access_Start_Sig,

Read_Data,

Words_Addr,

Write_Data

);

input CLK;

input RSTn;

input [7:0]Start_Sig;

output Done_Sig;

input [7:0]Time_Write_Data;