IS61LPD51218A-250B3I中文资料(18)

元器件交易网

IS61VPD25636A,IS61VPD51218A, IS61LPD25636A, IS61LPD51218A

SNOOZE MODE ELECTRICAL CHARACTERISTICS

SymbolISB2tPDStPUStZZItRZZI

Parameter

Current during SNOOZE MODEZZ active to input ignoredZZ inactive to input sampledZZ active to SNOOZE currentZZ inactive to exit SNOOZE current

ConditionsZZ ≥ Vih

Min.——2—0

Max.602—2—

ISSI

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SNOOZE MODE TIMING

元器件交易网

IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A

IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)

The IS61LPD/VPD25636A and IS61LPD/VPD51218A havea serial boundary scan Test Access Port (TAP) in the PBGApackage only. (The TQFP package not available.) This portoperates in accordance with IEEE Standard 1149.1-1900,but does not include all functions required for full 1149.1compliance. These functions from the IEEE specification areexcluded because they place added delay in the criticalspeed path of the SRAM. The TAP controller operates in amanner that does not conflict with the performance of otherdevices using 1149.1 fully compliant TAPs. The TAPoperates using JEDEC standard 2.5V I/O logic levels.

ISSI

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TEST ACCESS PORT (TAP) - TEST CLOCK

The test clock is only used with the TAP controller. Allinputs are captured on the rising edge of TCK and outputsare driven from the falling edge of TCK.

TEST MODE SELECT (TMS)

The TMS input is used to send commands to the TAPcontroller and is sampled on the rising edge of TCK. Thispin may be left disconnected if the TAP is not used. Thepin is internally pulled up, resulting in a logic HIGH level.

TEST DATA-IN (TDI)

The TDI pin is used to serially input information to theregisters and can be connected to the input of anyregister. The register between TDI and TDO is chosen bythe instruction loaded into the TAP instruction register.For information on instruction register loading, see theTAP Controller State Diagram. TDI is internally pulled upand can be disconnected if the TAP is unused in anapplication. TDI is connected to the Most Significant Bit(MSB) on any register.

DISABLING THE JTAG FEATURE

The SRAM can operate without using the JTAG feature. Todisable the TAP controller, TCK must be tied LOW (Vss) toprevent clocking of the device. TDI and TMS are internallypulled up and may be disconnected. They may alternatelybe connected to VDD through a pull-up resistor. TDO shouldbe left disconnected. On power-up, the device will start in areset state which will not interfere with the device operation.

TAP CONTROLLER BLOCK DIAGRAM