IS61LPD51218A-250B3I中文资料(6)

元器件交易网

IS61VPD25636A,IS61VPD51218A, IS61LPD25636A, IS61LPD51218A

165 PBGA PACKAGE PIN CONFIGURATION

256K X 36 (TOP VIEW)

1ABCDEFGHJKLMNPR

NCNCDQPcDQcDQcDQcDQcNCDQdDQdDQdDQdDQPdNCMODE

2AANCDQcDQcDQcDQcVssDQdDQdDQdDQdNCNCNC

3CECE2VDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

4BWcBWdVssVDDVDDVDDVDDVDDVDDVDDVDDVDDVssAA

5BWbBWaVssVssVssVssVssVssVssVssVssVssNCTDITMS

6CE2CLKVssVssVssVssVssVssVssVssVssVssNCA1*A0*

7BWEGWVssVssVssVssVssVssVssVssVssVssNCTDOTCK

8ADSCOEVssVDDVDDVDDVDDVDDVDDVDDVDDVDDVssAA

9ADVADSPVDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

10AADQbDQbDQbDQbNCDQaDQaDQaDQaAA

ISSI

11NCNCDQbDQbDQbDQbZZDQaDQaDQaDQaAA

®

DQPb

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst isdesired.

PIN DESCRIPTIONS

SymbolAA0, A1ADVADSPADSCGWCLK

CE, CE2, CE2

Pin Name

Address Inputs

Synchronous Burst Address InputsSynchronous Burst AddressAdvance

Address Status ProcessorAddress Status ControllerGlobal Write EnableSynchronous ClockSynchronous Chip Select

SymbolBWEOEZZMODETCK, TDOTMS, TDINCDQxDQPxVDDVDDQ

Vss

Pin NameByte Write EnableOutput EnablePower Sleep ModeBurst Sequence SelectionJTAG Pins

No Connect

Data Inputs/OutputsData Inputs/Outputs3.3V/2.5V Power Supply

Isolated Output Power Supply3.3V/2.5VGround

BWx (x=a,b,c,d)Synchronous Byte Write

Controls