IS61LPD51218A-250B3I中文资料(20)

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IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A

TAP INSTRUCTION SET

Eight instructions are possible with the three-bit instructionregister and all combinations are listed in the InstructionCode table. Three instructions are listed as RESERVEDand should not be used and the other five instructions aredescribed below. The TAP controller used in this SRAM isnot fully compliant with the 1149.1 convention becausesome mandatory instructions are not fully implemented.The TAP controller cannot be used to load address, data orcontrol signals and cannot preload the Input or Outputbuffers. The SRAM does not implement the 1149.1 com-mands EXTEST or INTEST or the PRELOAD portion ofSAMPLE/PRELOAD; instead it performs a capture of theInputs and Output ring when these instructions are executed.Instructions are loaded into the TAP controller during theShift-IR state when the instruction register is placedbetween TDI and TDO. During this state, instructions areshifted from the instruction register through the TDI andTDO pins. To execute an instruction once it is shifted in,the TAP controller must be moved into the Update-IRstate.

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SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction.The PRELOAD portion of this instruction is not imple-mented, so the TAP controller is not fully 1149.1 compli-ant. When the SAMPLE/PRELOAD instruction is loadedto the instruction register and the TAP controller is in theCapture-DR state, a snapshot of data on the inputs andoutput pins is captured in the boundary scan register.It is important to realize that the TAP controller clockoperates at a frequency up to 10 MHz, while the SRAMclock runs more than an order of magnitude faster.Because of the clock frequency differences, it is possiblethat during the Capture-DR state, an input or output willunder-go a transition. The TAP may attempt a signalcapture while in transition (metastable state). The devicewill not be harmed, but there is no guarantee of the valuethat will be captured or repeatable results.

To guarantee that the boundary scan register will capturethe correct signal value, the SRAM signal must bestabilized long enough to meet the TAP controller’scapture set-up plus hold times (tCS and tCH). To insure thatthe SRAM clock input is captured correctly, designs needa way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not an issue, it is possibleto capture all other signals and simply ignore the value ofthe CLK and CLK captured in the boundary scan register.Once the data is captured, it is possible to shift out the databy putting the TAP into the Shift-DR state. This places theboundary scan register between the TDI and TDO pins.Note that since the PRELOAD part of the command is notimplemented, putting the TAP into the Update to the Update-DRstate while performing a SAMPLE/PRELOAD instructionwill have the same effect as the Pause-DR command.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to beexecuted whenever the instruction register is loaded withall 0s. Because EXTEST is not implemented in the TAPcontroller, this device is not 1149.1 standard compliant.The TAP controller recognizes an all-0 instruction. Whenan EXTEST instruction is loaded into the instructionregister, the SRAM responds as if a SAMPLE/PRELOADinstruction has been loaded. There is a difference betweenthe instructions, unlike the SAMPLE/PRELOAD instruction,EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bitcode to be loaded into the instruction register. It alsoplaces the instruction register between the TDI and TDOpins and allows the IDCODE to be shifted out of the devicewhen the TAP controller enters the Shift-DR state. TheIDCODE instruction is loaded into the instruction registerupon power-up or whenever the TAP controller is given atest logic reset state.

BYPASS

When the BYPASS instruction is loaded in the instructionregister and the TAP is placed in a Shift-DR state, thebypass register is placed between the TDI and TDO pins.The advantage of the BYPASS instruction is that itshortens the boundary scan path when multiple devicesare connected together on a board.

SAMPLE-Z

The SAMPLE-Z instruction causes the boundary scanregister to be connected between the TDI and TDO pinswhen the TAP controller is in a Shift-DR state. It alsoplaces all SRAM outputs into a High-Z state.

RESERVED

These instructions are not implemented but are reservedfor future use. Do not use these instructions.