IS61LPD51218A-250B3I中文资料(7)

元器件交易网

IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A

165 PBGA PACKAGE PIN CONFIGURATION

512K X 18 (TOP VIEW)

1

ABCDEFGHJKLMNPR

NCNCNCNCNCNCNCNCDQbDQbDQbDQbDQPbNCMODE

2AANCDQbDQbDQbDQbVssNCNCNCNCNCNCNC

3CECE2VDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

4BWbNCVssVDDVDDVDDVDDVDDVDDVDDVDDVDDVssAA

5NCBWaVssVssVssVssVssVssVssVssVssVssNCTDITMS

6CE2CLKVssVssVssVssVssVssVssVssVssVssNCA1*A0*

7BWEGWVssVssVssVssVssVssVssVssVssVssNCTDOTCK

8ADSCOEVssVDDVDDVDDVDDVDDVDDVDDVDDVDDVssAA

9ADVADSPVDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

10AANCNCNCNCNCNCDQaDQaDQaDQaNCAA

ISSI

11ANCDQPaDQaDQaDQaDQaZZNCNCNCNCNCAA

®

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst isdesired.

PIN DESCRIPTIONS

SymbolAA0, A1ADVADSPADSCGWCLK

CE, CE2, CE2BWx (x=a,b)

Pin Name

Address Inputs

Synchronous Burst Address InputsSynchronous Burst AddressAdvance

Address Status ProcessorAddress Status ControllerGlobal Write EnableSynchronous ClockSynchronous Chip SelectSynchronous Byte WriteControls

SymbolBWEOEZZMODETCK, TDOTMS, TDINCDQxDQPxVDDVDDQ

Vss

Pin Name

Byte Write EnableOutput EnablePower Sleep ModeBurst Sequence SelectionJTAG Pins

No Connect

Data Inputs/OutputsData Inputs/Outputs3.3V/2.5V Power Supply

Isolated Output Power Supply3.3V/2.5VGround