IS61LPD51218A-250B3I中文资料(4)

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IS61VPD25636A,IS61VPD51218A, IS61LPD25636A, IS61LPD51218A

119 BGA PACKAGE PIN CONFIGURATION-256K X 36 (TOP VIEW)

1

ABCDEFGHJKLMNPRTU

VDDQNCNCDQcDQcVDDQDQcDQcVDDQDQdDQdVDDQDQdDQdNCNCVDDQ

2ACE2ADQPcDQcDQcDQcDQcVDDDQdDQdDQdDQdDQPdANCTMS

3AAAVssVssVssBWcVssNCVssBWdVssVssVssMODEATDI

4ADSPADSCVDDNCCEOEADVGWVDDCLKNCBWEA1*A0*VDDATCK

5AAAVssVssVssBWbVssNCVssBWaVssVssVssNCATDO

6

7

ISSI

®

AVDDQAADQPb DQbDQbDQbDDQDQbDQbVDDDDQDQaDQaDQa VDDQDQa DQaDQPa DQaANC ZZNCDDQ

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

AA0, A1ADVADSPADSCGWCLKCE, CE2BWx (x=a-d)BWE

Pin Name

Address Inputs

Synchronous Burst Address InputsSynchronous Burst AddressAdvance

Address Status ProcessorAddress Status ControllerGlobal Write EnableSynchronous ClockSynchronous Chip SelectSynchronous Byte Write ControlsByte Write Enable

SymbolOEZZMODETCK, TDO TMS, TDINCDQa-DQdDQPa-PdVDDVDDQVss

No ConnectData Inputs/OutputsOutput Power SupplyPower SupplyOutput Power SupplyGroundPin NameOutput EnablePower Sleep ModeBurst Sequence SelectionJTAG Pins